1. Field of the Invention
The present invention relates to a semiconductor device and to a method of manufacturing the same and, more particularly, to a semiconductor device having a self-align contact structure used in DRAM, etc. and to a method of manufacturing the same.
2. Description of the Prior Art
An element area in the semiconductor device is required to reduce, as the integration of the semiconductor device becomes higher. However, under the prior art, an alignment precision in the photolithography cannot be so improved as the requirement of the size reduction of the semiconductor device.
Thus, various techniques have been taken with the miniaturization of the semiconductor device. For example, the self-align contact used in the highly integrated semiconductor memory device such as DRAM (dynamic random access memory) is adopted.
In the self-align contact, the silicon nitride film is formed on the side faces of the gate electrode as the sidewall spacer. The self-align contact that is constructed by forming the sidewall spacer made of silicon nitride on the side faces of the gate electrode of the MOS transistor will be explained hereunder.
First, a manufacturing method of the structure shown in FIG. 1A will now be explained.
The active regions in the memory cell region 102 and the peripheral circuit region 103 on the silicon substrate 101 respectively are isolated by an isolation insulating film 104. Then, the wells 105, 106 are formed by implanting the impurity ion into predetermined active regions of the silicon substrate 101 and by using a mask.
Next, the gate insulating films 107 are formed in the active regions by the thermal oxidation method, and then a silicon film and a protection insulating film are formed sequentially by the chemical vapor deposition (CVD) method. Then, gate electrodes 108a, 108b are formed in the memory cell region 102 and the peripheral circuit region 103 by patterning a silicon film and a protection insulating film by virtue of the photolithography method. In this case, the gate electrodes 108a are formed in one active region in the memory cell region 102 at the predetermined interval.
In this case, upper surfaces of the gate electrodes 108a, 108b are covered with the protection insulating film 109.
Next, steps to get the state shown in FIG. 1B will now be explained.
First, low impurity concentration portions of the impurity diffusion layers 110a, 110b are formed on both sides of the gate electrodes 108a, 108b on the silicon substrate 101 by ion-implanting the impurity into the active regions while using the gate electrodes 108a, 108b and the isolation insulating film 104 as a mask.
Then, a silicon nitride film for covering the gate electrodes 108a, 108b and the isolation insulating film 104 is formed on the silicon substrate 101. Then, the silicon nitride film is left on both sides of the gate electrodes 108a, 108b as the sidewall spacers 11a, 111b by etching-back the silicon nitride film.
Then, high impurity concentration portions of the impurity diffusion layers 110a, 110b are formed by ion-implanting the impurity into the active regions while using the gate electrodes 108a, 108b and the sidewall spacers 111a, 111b as a mask.
Next, as shown in FIG. 1C, the first insulating film 112 and the second insulating film 113 for covering the gate electrodes 108a, 108b are formed in sequence. The silicon nitride film is formed as the first insulating film 112, and the silicon oxide film containing the impurity, e.g., BPSG (Boro-Phospho Silicate Glass) is formed as the second insulating film 113. The reason for forming the silicon nitride film under the BPSG is to prevent the diffusion of the impurity in BPSG into the silicon substrate 101. The second insulating film 113 is heated to reflow and planarize its upper surface.
Then, as shown in FIG. 1D, the contact holes 113a to 113c are formed on the impurity diffusion layers 110a existing in the memory cell region 102 by patterning the first insulating film 112 and the second insulating film 113 by using the photolithography method. In this case, the second insulating film 113 in the memory cell region 102 is etched by the hydrofluoric acid, and the first insulating film 112 acts as an etching stopper. Also, the first insulating film 112 is etched by the phosphoric acid to expose the underlying impurity diffusion layer 110b. 
The widths of these contact holes 113a to 113c are decided by intervals between the sidewall spacers 111a. 
In this case, in one memory cell region 102, the contact hole 113a formed in the center is used to connect the bit lines, and other two contact holes 113b, 113c are used to connect the capacitors.
Next, as shown in FIG. 1E, silicon plugs 114a to 114c are filled into the contact holes 113a to 113c. Then, the third insulating film 115 made of silicon oxide is formed on the second insulating film 113 and the plugs 114a to 114c. Then, the opening 116 is formed on the contact hole 113a for bit-line connection by patterning the third insulating film 115 by virtue of the photolithography method, and at the same time the contact hole 117 is formed on the impurity diffusion layer 110b by patterning the third insulating film 115 and the second insulating film 113 in the peripheral circuit region 103 by virtue of the photolithography method.
In forming the contact hole 117, control of the depths of the opening 116 and the contact hole 117 can be facilitated since the first insulating film 112 and the plug 114a function as the etching stopper. Therefore, in order to expose the impurity diffusion layer 110b from the contact hole 117, the first insulating film 112 must be etched via the contact hole 117.
Here, the Ixe2x80x94I sectional shape in FIG. 1E is shown in FIG. 3A.
After this, as shown in FIG. 1F, the metal film is formed on the third insulating film 115. Then, if this metal film is patterned, the bit line 118 connected to the plug 114a under the opening 116 is formed in the memory cell region 102 and also the wiring 119 connected to the impurity diffusion layer 110b via the contact hole 117 is formed in the peripheral circuit region 103.
Then, although not shown particularly, the steps of forming a capacitor (not shown) on the memory cell region 102 will be carried out.
Other wirings of the gate electrode are formed in the peripheral circuit region 103. In this case, in order to connect the wirings and the overlying wiring, the structure shown in FIG. 4 is adopted.
Next, the steps of forming the structure shown in FIG. 4 will be explained.
First, the device isolation insulating film 132 is formed on the surface of the silicon substrate 131. Then, a plurality of gate electrodes 134, 135 are formed in the memory cell region 102 and the peripheral circuit region 103 via the gate oxide film 133 respectively. At the same time, the first layer wiring 136 passing through over the device isolation insulating film 132 is formed in the peripheral circuit region 103.
These gate electrodes 134, 135 and the first layer wiring 136 have a double-layered structure that consists of a polysilicon film and a tungsten silicide film respectively. The protection insulating film 137 made of the silicon nitride film is formed thereon.
Then, the silicon nitride film is formed to cover the gate electrodes 134, 135, the first layer wiring 136, and the silicon substrate 131. Then, sidewall spacers 138a, 138b, 138c are left on both sides of the gate electrodes 134, 135 and the first layer wiring 136 respectively by etching-back the silicon nitride film. The first layer wiring 136 has the structure that is extended from the gate electrode 135 to the device isolation insulating film 132.
The impurity diffusion layers 139a, 139b serving as the source/drain are formed by introducing the impurity into the silicon substrate 131 before and after the sidewall spacers 138a, 138b, 138c are formed.
Then, the first interlayer insulating film 140 made of BPSG is formed on the protection insulating film 137, the semiconductor substrate 131, etc. The surface of the first interlayer insulating film 140 is planarized by heating to reflow or by the chemical mechanical polishing.
In the memory cell region 102, the contact holes 141a, 141b are formed for bit-line contact and storage contact, by etching a part of the first interlayer insulating film 140. These contact holes 141a, 141b are formed as the self-align contacts that are positioned between the gate electrodes 134 in a self-alignment fashion.
In addition, the plugs 142a, 142b made of silicon are formed in the contact holes 141a, 141b in the memory cell region 102. Then, the second interlayer insulating film 143 made of the silicon oxide film is formed on the plugs 142a, 142b and the first interlayer insulating film 140. Then, the hole 143a for bit-line connection is formed by etching the second interlayer insulating film 143 on the plug 142a for bit-line connection in the memory cell region 102. At the same time, the contact hole 144 is formed by etching the first interlayer insulating film 140 and the second interlayer insulating film 143 on the impurity diffusion layer 139b in the peripheral circuit region 103.
Thereafter, the bit line 145a passing through an inside of the hole 143a is formed in the memory cell region 102 and at the same time second layer wirings 145b, 145c are formed in the peripheral circuit region 103. A part of the pattern of the second layer wiring 145b is connected to the impurity diffusion layer 139b via the contact hole 144.
In this case, the bit line 145a and the second layer wiring 145b are formed of the metal film that has the triple-layered structure of Ti/TiN/W, for example.
Then, the third interlayer insulating film 146 made of the silicon oxide film or BPSG is formed, and then the surface of the third interlayer insulating film 146 is planarized by the chemical mechanical polishing.
Then, the capacitor is formed in the memory cell region 102. Here, the cylinder-shaped capacitor is illustrated as an example. The capacitor is formed along with following steps.
First, the storage contact hole 147a is opened by etching the second interlayer insulating film 143 and the third interlayer insulating film 146 formed on the storage contact plug 142b in the memory cell region 102, and then the plug 148 made of impurity containing silicon is formed in the hole 147a. 
The fourth interlayer insulating film 147 made of the silicon nitride film is formed on the plug 148 and the third interlayer insulating film 146. Then, the patterning insulating film (not shown) made of the silicon oxide film or BPSG is formed on the fourth interlayer insulating film 147, and then the opening having the capacitor shape is formed by patterning the patterning insulating film and the fourth interlayer insulating film 147 by virtue of the photolithography method. Then, the polysilicon film is formed on the inner surface of the opening and on the patterning insulating film, and then the polysilicon film 150 on the patterning insulating film is removed by the chemical mechanical polishing. In this polishing, the photoresist may be filled into the concave portion formed by the polysilicon film in the opening of the patterning insulating film.
Accordingly, the polysilicon film being left like the cylinder in the opening of the patterning insulating film is used as the storage electrode 150 of the capacitor.
Then, the outer peripheral surface and the inner peripheral surface of the cylindrical storage electrode 150 are exposed by removing the patterning insulating film by using the hydrofluoric acid. According to difference in material, it is feasible to etch selectively the patterning insulating film with respect to the fourth interlayer insulating film 147.
Then, the dielectric film 151 made of tantalum oxide is formed on the surface of the storage electrode 150 by the chemical vapor deposition method, and then the opposing electrode 152 is formed on the dielectric film 151. The opposing electrode 152 is composed of the double-layered structure of titanium and polysilicon, for example. Accordingly, the capacitor 153 is completed.
After this, the fifth interlayer insulating film 149 as the silicon oxide film for covering the capacitor 153 is formed on the fourth interlayer insulating film 147, and then the surface of the fifth interlayer insulating film 149 is made flat by the chemical mechanical polishing.
Then, the via hole 154a is formed by etching the third to fifth interlayer insulating films 146, 147, 149 on the second layer wiring 145c in the peripheral circuit region 103 by means of the photolithography method. Also, the via hole 154b is formed by etching the first to fifth interlayer insulating films 140, 143, 146, 147, 149 and the protection insulating film 137 on the first layer wiring 145b in the peripheral circuit region 103. At this time, the holes are formed on the bit line 145a and the opposing electrode 152 respectively, but such holes are omitted from FIG. 4.
Then, the metal film having the triple-layered structure of Ti/TiN/W is formed in the via holes 154a, 154b and on the fifth interlayer insulating film 149. The metal film having the triple-layered structure being formed on the fifth interlayer insulating film 149 is removed by the chemical mechanical polishing method. Accordingly, the metal film having the triple-layered structure being left in the via holes 154a, 154b are used as the plugs 155a, 155b. At this time, the plugs are also formed in the holes (not shown) on the bit line 145a and the opposing electrode 152 in the memory cell region 102.
Thereafter, the third layer wirings 156, 157 made of an aluminum single layer or an aluminum containing non-stacked layer are formed on the fifth interlayer insulating film 149.
Here, the plugs 155a, 155b are electrically connected via the third layer wiring 156.
In this case, another third wiring 157 is formed in the memory cell region 102, and a part of the third wiring 157 is connected to the bit line 145a, the opposing electrode 512, etc. via the plugs (not shown).
The above steps are forming method of the memory cell and the peripheral circuit. FIG. 5A is a plan view showing arrangement relationship between the bit line 145a, the third layer wiring 157, etc. in the memory cell region 102. FIG. 5B is a plan view showing arrangement relationship between the wirings, etc. in the peripheral circuit region 103. The memory cell region 102 shown in FIG. 4 is a sectional shape that is viewed along a Xxe2x80x94X line in FIG. 5A. The peripheral circuit region 103 shown in FIG. 4 is a sectional shape that is viewed along a XIxe2x80x94XI line in FIG. 5B.
By the way, based on the steps of forming the contact holes 113a to 113c shown in FIGS. 1A to 1F, there is such a possibility that the forming position of the contact hole 113a for bit-line connection is displaced and thus is separated from the sidewall spacer 111a on one side, as shown in FIG. 2A.
If the alignment displacement is caused in forming the contact hole 113a for bit-line connection and also the overlying opening 116 formed in the third insulating film 115 is formed at the normal position, the underlying first insulating film 112 is etched successively in forming the opening portion 116 in the second insulating film 113. Thus, as shown in FIG. 2B, the clearance 120 is formed on the side of the plug 114a to expose a part of the impurity diffusion layer 110a. 
If the bit line 118 is formed on the third insulating film 115 under such state, such bit line 118 reaches the impurity diffusion layer 110a via the clearance 120, as shown in FIG. 2C. The IIxe2x80x94II line sectional shape in FIG. 2C is shown in FIG. 3B.
Then, when the bit line 118 is connected to the impurity diffusion layer 110a, the bit-line constituting metal element enters into the impurity diffusion layer 110a in the later heating step to increase the leakage current from the impurity diffusion layer 110a, and therefore the charge storage of the capacitor is badly influenced. The slight leakage current from the impurity diffusion layer 110b does not become a serious issue in the peripheral circuit region 103.
On the contrary, the method of forming widely the upper surface region of the plug 114a may be considered as the countermeasure for the alignment displacement. In this case, another disadvantage such that the higher integration becomes difficult is caused. For the space between the plugs must be maintained at a predetermined interval to assure the breakdown voltage between the neighboring plugs and thus the increase in the upper surface region of the plug interferes with the higher integration of the semiconductor device.
Also, in the above method, only the identical widths can be selected in the memory cell region 102 and the peripheral circuit region 103 as the film thicknesses of the sidewall spacers 111a, 111b formed on both sides of the gate electrodes 108a, 108b. Therefore, the optimization of both the self-align contact breakdown voltage in the memory cell region and the widths of the sidewall spacers on the side surfaces of the gate electrode of the transistor in the peripheral circuit region cannot be achieved simultaneously. Thus, there is caused such a problem that the higher integration of the semiconductor device and the optimization of the driving characteristic of the transistor are not compatible.
In the meanwhile, in the semiconductor memory device shown in FIG. 4, the second layer wiring 145c and the first layer wiring 136 are connected to each other via the wiring 156 being formed on the fifth interlayer insulating film 149. The reason for this is given as follows.
First, in the step of forming the hole 143a to connect the bit line 145a and the underlying plug 142a in the memory cell region 102 and the contact hole 144 to connect the second layer wiring 145b and the impurity diffusion layer 139b in the peripheral circuit region 103, it is preferable that the contact hole to connect the first layer wiring 136 and the overlying second layer wiring 145c in the peripheral circuit region 103 should be formed simultaneously.
In case three type holes are opened simultaneously, the silicon nitride film acting as the protection insulating film 137 on the first layer wiring 136 must be etched.
However, when the hole 143a to connect the bit line 145a and the plug 142a is formed in the memory cell region 102, the displacement margin cannot be sufficiently assured because of the request of miniaturization. As a result, the forming position of the hole 143a protrudes from the plug 142a. Then, if the protection insulating film 137 is etched via the hole 143a that protrudes from the plug 142a, the breakdown voltage between the plug 142a and the gate electrode 134 is deteriorated. In the worst case, the short-circuit between the plug 142a and the gate electrode 134 is brought about.
Then, at the time of anisotropic etching of the second interlayer insulating film 143 in which the hole 143a is formed, such a condition is employed that the selective etching ratio of the second interlayer insulating film 143 to the protection insulating film 137 is consciously set high. As the anisotropic etching condition, the etching in the mixed gas atmosphere consisting of C4F8, CHF3, Ar, O2, etc., for example, may be considered.
Accordingly, if the hole 143a is displaced from the plug 142a, the protection insulating film 137 is hardly etched, so that the exposure of the gate electrode 134 from the hole 143a can be prevented.
According to the above reason, it is not applied to etch successively the first interlayer insulating film 140 and the protection insulating film 137, both are formed of different material. Assume that the hole to connect the second layer wiring 145c and the first layer wiring 136 is formed in the second interlayer insulating film 143, the first interlayer insulating film 140, and the protection insulating film 137 in the peripheral circuit region 103, the step of forming the resist mask that is used to etch only the protection insulating film 137 on the first layer wiring 136 is needed after the etching of the first interlayer insulating film 140 is finished. Thus, it is impossible to avoid the complication of the steps.
In contrast, when the holes are formed in the fifth interlayer insulating film 149 and the underlying interlayer insulating films, there is no possibility that the protection insulating film 137 in the memory cell region 102 since the formation of the holes 143a, 147a connected to the plugs 141a, 141b in the memory cell region 102 has already been finished. Therefore, after the etching of the first interlayer insulating film 140 is finished, the protection insulating film 137 on the first layer wiring 136 can be etched by changing the etching conditions, without the change of the mask.
According to the above, the structure that the first layer wiring 136 and the second layer wiring 145c are electrically connected to each other via the wiring 156 formed on the fifth interlayer insulating film 149 and the holes 154a, 154b is employed.
However, if such structure is employed, the connecting portions between the first layer wiring 136 and the second layer wiring 145c must be formed separately and also the wiring 156 to connect these wirings 136, 145c must be formed. Therefore, there is the problem such that the chip area is increased at this time.
It is an object of the present invention to provide a semiconductor device capable of suppressing increase in a leakage current from impurity diffusion layers connected to plugs even if mutual positions of the plugs and bit-line opening portions are displaced in the process by which a window connected to a bit line in the memory cell region and windows connected to source/drain impurity diffusion layers of a transistor in the peripheral circuit region are opened simultaneously, in the case that metal material is used as the bit line, and also capable of assuring optimum widths of sidewall spacers on side surfaces of gate electrodes in a memory cell region and a peripheral circuit region respectively, and a method of manufacturing the same.
Also, it is another object of the present invention to provide a semiconductor device capable of connecting multi-layered wirings by a small number of steps, and a method of manufacturing the same.
Accordingly, if the first holes are formed to displace to the gate electrode on one side in the first region and also the second hole being formed simultaneously with the third hole is formed to protrude from the first holes, the semiconductor substrate is never exposed from the second hole because of the presence of the first insulating film. Therefore, even if the metal film is formed in the second hole, the connection between the metal film and the impurity diffusion layer on the semiconductor substrate can be prevented in the first region.
In addition, the first insulating film is formed to have an optimum thickness to form the spacers on the side surfaces of the gate electrodes in the second region, and thus the total film thickness of the first and second insulating films can be selected to give the optimum thickness as the spacers on the side surfaces of the gate electrodes in the first region.
Accordingly, the optimization of the film thickness of the spacers on the side surfaces of the gate electrodes can be selected every region.
Also, according to the above invention, in the case that the first holes that are formed in the insulating film between the gate electrodes in the first region are formed to deviate to the gate electrodes on one side and the plugs are formed in the first holes and also the second hole that is formed in the overlying insulating film covering the plugs is displaced from the plugs and has a depth reaching the impurity diffusion layer on the semiconductor substrate, the burying insulating film is formed selectively on the portions being projected from the plugs in the second hole.
Accordingly, the metal film formed in the second hole is never connected to the impurity diffusion layer because of the burying insulating film.
Accordingly, the holes can be simultaneously formed on the plugs in the first region and on the gate electrodes and the first layer wiring in the second region respectively without change of the etchant by patterning the second insulating film and the third insulating films. Therefore, throughput of the hole formation can be improved.